1. Field of the Invention
The present invention relates to an apparatus and method for minimizing clock skew. More particularly, the present invention relates to a circuit within a bus bridge having at least first and second clock domains, wherein the circuit allows information to be reliably transferred between the first and second clock domains regardless whether or not an internal bus clock of the second clock domain is synchronized with an internal bus clock of the first domain, while still minimizes clock skew between each of the internal bus clocks as well as any corresponding external bus clocks.
2. Background of the Invention
It is commonly known that several clock domains (i.e., portions of a system using a particular clocking frequency) can be used throughout a computer system. These clock domains allow various components to operate at their most efficient level. A bus bridge is an apparatus which enables any information, particularly data or address information (hereinafter collectively referred to as "data/address information") to be transferred from a first bus to a second bus, wherein both the first and second buses utilize unique protocol i.e., timing and read/write commands. The data/address information can be transferred in a bi-directional manner, namely, from the first bus to the second bus and from the second bus to the first bus.
In conventional bus bridges, it is required that the first and second buses operate at identical or harmonically related frequencies. According to FIG. 1, a conventional bus bridge 1 is typically interposed between a faster, central processing unit ("CPU") bus 2 and a slower, peripheral component interconnect "CPU" bus 3. These buses are normally incorporated within a computer system 4 in which the CPU bus 2 enables communication between a plurality of processing devices 5a-5n operating at a first predetermined frequency and the PCI bus 3 enables communication between a plurality of peripheral devices 8a-8n (e.g., a video adapter 8a, hard disk drive controller 8n and the like) operating at a second predetermined frequency.
As shown in FIG. 1, the plurality of processing devices 5a-5n are clocked by a first external clock generator 6, which generates multiple copies of a CPU clock signal having the first predetermined frequency. These copies of the CPU clock signal are then utilized by the plurality of processing devices 5a-5n, in addition to any other device coupled to the CPU bus 2, including the conventional bus bridge 1. However, no external clock generator is needed in order to obtain a PCI clock signal having the second predetermined frequency. The reason being that the plurality of processing devices 5a-5n always operates at speeds greater than any of the plurality of peripheral devices 8a-8n. Thus, the first frequency is greater than the second frequency, allowing the CPU clock signal to be used to generate the PCI clock signal.
The PCI clock signal is obtained by inputting the CPU clock signal through deskewing logic and a "divide-by-n" divider incorporated with the bus bridge 1, where "n" is a whole number greater than zero. As a result, the second frequency is always harmonically related to the first frequency. The PCI clock signal is then inputted into an external clock driver 7, which generates multiple copies of the PCI clock signal to be used by every device operating on the PCI bus 3.
In the conventional bus bridge 1, deskewing is accomplished by employing the external clock driver 7 into a feedback relationship with the bus bridge 1. The feedback relationship consists of inputting one copy of the PCI clock signal back into the bus bridge 1 and then using a conventional phase-locked loop to deskew and to align the clock edges of the PCI clock signal with the CPU clock signal bridge clocking.
One problem associated with the conventional bus bridge is that it is not able to support the CPU clock signal.
Another problem associated with the conventional bus bridge is that it imposed limitations on system design because the second frequency used by the PCI devices is required to be harmonically related to the first frequency used by the processing devices.
Yet another problem is that the conventional bus bridge imposes performance limitations since the PCI bus clock is required to be harmonically related to the CPU bus clock. For example, if the maximum CPU clock frequency is sixty megahertz (60 MHz) and the maximum PCI clock frequency is twenty-three megahertz (23 MHz), the conventional bus bridge would require a complex combination of dividers, multipliers and the like in order to enable the CPU and PCI clocks to function at their maximum levels. Such complexity could cause delay problems.
In addition to developing a clocking relationship between the clock domains, there exists an equally important need to ensure that data/address information is reliably transferred between clock domains. Normally, transferring data/address information from the first bus to the second bus is a four-step process. The first step is transferring the data/address information into an intermediate buffering device (e.g., a FIFO). Then, notifying interface logic for the second bus that the data/address information has been placed into the buffering device. Such notification is accomplished by a conventional synchronizer being a pair of cascaded flip-flops clocked at the second bus frequency. Next, the interface logic of the second bus obtains the data/address information from the intermediate buffering device. Finally, the interface logic of the second bus notifies interface logic of the first bus that the buffering device is now empty and available. However, there is no protocol for transferring data/address information in bus circuit supporting both synchronous and asynchronous operations.